Computer Processor Implementation

The basic implementation of a processor revolves around the performance of a computer. Three factors play a role in the performance of a computer such as instruction count, clock cycle time, and clock cycles per instruction. According to the textbook, it mentions, "the implementation of the processor determines both the clock cycle time and the number of clock cycles per instruction." The MIPS instruction sets pertain to fetching the program counter's memory address and reading from the registers.  

The ALU, adder, instruction, data memory, and the register file are all needed for the MIPS data path. The instruction and data memory are used to store the instruction location. In other words, the data path and the instruction memory get the instructions from the program counter along with the adder. Then the program counter is incremented to the following instruction location. These two elements are considered state elements because they can store information. The ALU and adder are considered combinational elements. Combinational elements can be defined as something that "always produces the same value" (Patterson & Hennessy, 2014). Pipelining is the process of accumulating instruction from the processor through a pipeline. It allows storing and executing instructions in an orderly process. It is also known as pipeline processing. 

Pipelining is a technique where multiple instructions are overlapped during execution. When pipelining is introduced into a single cycle data path, it rapidly speeds up the execution of instructions. This is because of the overlapping instruction. Instead of waiting for all the stages to be complete before starting the next instruction, the instruction is overlapped, so more instructions are executed per clock cycle. 

References:

Patterson, D. A., & Hennessy, J. L. (2014). Computer organization and design: The hardware/software interface (5th ed.). Retrieved from https://zybooks.zyante.com/#/zybook/jCx8rOUvAL/gettingstarted